A major hurdle in the production of high performance computers is the electrical and thermal packaging for very large scale integration (VLSI) and ultra large scale integration (ULSI) chips. While high performance VLSI and ULSI chips have been designed to include up to several million devices thereon, a major problem still exists in connecting these chips together and dissipating the heat produced. A high performance integrated circuit chip package must provide for high density electrical interconnection and thermal stability of integrated circuit chips.
It will be recognized that the electrical and thermal performance of integrated circuit packaging may represent conflicting design parameters. For example, an increase in package size may decrease the heat dissipation capability required per unit area. However such an increase in package size will increase the path length between chips and thereby increase the propagation delay. On the other hand, placing the chips closer together maximizes speed while requiring a large number of chip connections in a small area and high heat dissipation per unit area.
One well known high performance chip package is the Thermal Conduction Module (TCM), which is described in U.S. Pat. No. 3,993,123 to Hugh et al., and in an article entitled "Thermal Conduction Module: A High Performance Multilayer Ceramic Package," by A. J. Blodgett and D. R. Barbour published in the IBM Journal of Research and Development, Vol. 26, No. 1, P30 (January 1982). The TCM includes a multilayer ceramic substrate which is capable of providing connections for about 100 integrated circuit chips, each dissipating up to a maximum of 3-4 watts. The substrate, formed of fired alumina ceramic, includes up to 33 internal wiring layers therein, and about 1800 brazed input/output pins on the bottom surface thereof for connecting to the next level of packaging. Integrated circuits are mounted on the top surface of the substrate, using the well known controlled collapse chip connection ("C-4"), or solder bump technology. A cylindrical piston is spring biased against the back of each chip to provide a heat conductive path to a water cooled housing consisting of a cover or hat and a cold plate, the cold plate having suitable chambers for circulation of water. A metal C-ring is compressed between the hat and substrate frame to form a hermetic seal, and helium gas is provided in the hermetically sealed area for further heat conduction.
While the TCM represents a significant advance in multi-chip packaging, there are a number of limitations therein which make it unsuitable for high power high density VLSI and ULSI chips. For example, power dissipation is limited to about 3-4 watts per chip notwithstanding the elaborate cooling scheme. The multilayer ceramic substrate also possesses a number of shortcomings. First, the alumina substrate has a coefficient of thermal expansion which is quite different from that of the silicon integrated circuit chips, resulting in sufficient thermal mismatch such that the size of the chip is severely limited. Use of larger chips would result in stress-related reliability problems. The C-4 joints between the integrated circuits and the substrate provide a buffer between the thermal mismatch; however, the inflexibility of these joints provides a limit as to the size of integrated circuit chips which may be employed. Moreover, in order to properly align the 30 or more layers of the multilayer ceramic substrate, the conductive lines and vias internal to the substrate must be thick. A large number of layers must therefore be formed to provide all of the conductors necessary for chip connections. The large number of layers and the vias connecting them result in significant unwanted inductances and capacitances. The large number of layers also create potential yield problems. Since the entire substrate must be formed before it may be tested, a defect in any internal layer requires the entire substrate to be scrapped. Finally, the piston and spring arrangement for heat removal creates large mechanical stresses on the chips and requires a hermetically sealed helium environment for added heat dissipation. This scheme also severely limits the heat removal capability of the package.
The art has provided many improvements on the basic TCM in an attempt overcome these shortcomings. For example, U.S. Pat. No. 4,092,697 to Spaight describes a TCM in which a thermal liquid material enclosed in a film is mounted between the chips and heat sink. U.S. Pat. No. 4,639,829 to Ostergrin et al. discloses a truncated solid conical piston which includes a thin layer of high thermal conductivity grease between the piston and heat sink for added heat dissipation. U.S. Pat. No. 4,617,730 to Geldermans et al. discloses a method of forming a chip interposer which is placed between a multilayer ceramic substrate and an integrated circuit chip to provide thin film redistribution interconnections. Finally, an article entitled "High Performance Heat Sinking for VLSI" published by D. B. Tuckerman and R. F. W. Pease in the IEEE Electron Device Letters, Volume EDL-2, No. 5, May, 1981, at page 126, discloses a use of a large number of small fluid channels for cooling an integrated circuit chip. Notwithstanding these and other improvements, the TCM does not provide a dense enough or powerful enough package for VLSI and for future generations of ULSI chips.